The present invention is related to the automated design of integrated circuit (IC) chips and, more particularly, to a method of physical planning voltage islands applicable to ASICs and System-on-a-Chip designs.
While meeting the timing requirements of modem System-on-a-Chip (SoC) designs is difficult, power consumption has become a critical design metric due to increasing power density and the wide use of portable systems. Many techniques are available for reducing power consumption, of which one of the most effective ones consists in lowering the voltage (VDD) because power consumption due to switching is proportional to VDD2 and the standby power consumption is proportional to VDD. However, lowering VDD leads to a reduced circuit performance, the amount of reduction being bound by the delay on the critical path which leaves most non-critical paths having a large slack.
A dual VDD approach has been described by K. Usami, et al., in the article “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998, pp. 463-472, which provides an initial solution to the above described problem by assigning a high VDD value to circuits on the critical path and a low VDD to circuits on the non-critical path. Extending the dual VDD concept necessitates the use of multiple VDDs to better address the power problem. The main problem when using multiple supplies is the distribution of power to the various voltage supplies. In a grid-style power distribution network, a fine-grained approach, such as a gate-based one is extremely difficult to achieve. In a coarse-grained approach, an RLM (Random Logic Macro) consisting of a group of cells, is made to operate at its own voltage, and the entire design is implemented by a plurality of RLMs operating at different voltages. This approach, while alleviating the problem of power distribution in the fine grained approach presents several problems such as: identifying partitions of circuits for a VDD assignment; characterizing each partition with respect to VDD; and floorplanning partitions such that those powered by the same VDD are grouped together. These grouping of partitions essentially lead to the formation of a voltage island, i.e., an independent region of a chip powered by its own power supply voltage.
The partitioning function applicable to a voltage island planning was introduced by D. E. Lackey, et al., “Managing Power and Performance for System-on-Chip Designs using Voltage Islands”, Proc. ICCAD 2002. However, its application is limited because partitions and floorplanning are assumed to be given. It merely explores different combinations of VDD to ensure that the timing is satisfied and power is minimized. If partitioning and floorplanning are not performed intelligently, the design space becomes significantly narrow. The number of partitions it can handle is limited as well, since the complexity of the approach grows exponentially.
Fine-grained voltage island techniques have been further described by R. Puri, et al., “Pushing ASIC Performance in a Power Envelope,” Proc. DAC, pp. 788-793, June 2003. These, however, are still limited to using two VDDs instead of many VDDs.
Introducing voltage islands complicates the chip design process even more with respect to static timing, power routing, floorplanning, and the like. The complexity grows significantly with the number of islands. Thus, a designer using voltage islands is required to group together cores (i.e., netlists consisting of pre-designed and pre-verified macros) powered by the same voltage source while ensuring that the group thus created does not violate other design metrics, such as timing and wiring congestion. Moreover, voltage islands need to be placed in close proximity to power pins in order to minimize the power routing complexity and the IR drop. Since each island requires its own power grid and level converters to communicate with different islands, the overhead related to area and delay becomes unavoidable. Additional area overhead may become available when using dead spaces when two or more cores are placed in the same island, although they cannot always be packed effectively. These additional requirements make the problem of generating the floorplan of a design consisting of voltage islands a unique one, a problem which is formulated and solved by the present invention. These problems have not been addressed in prior works in related areas.
Accordingly, there is a distinct need in the industry for a different approach to the above described problem. The voltage island planning is initiated very early in the design phase. This includes all the aforementioned problems, i.e., partitioning, characterizing, and floorplanning in the earlier stages of the design and which need to be solved in order to obtain a coarse grained voltage island solution for the automated design of integrated circuit chips.